1. Field of the Invention
The present invention relates in general to a nonvolatile memory device and a method for the fabrication of the same, and more particularly to improvements in a coupling ratio, a programming speed and an integration degree along with the nonvolatile memory device and the method.
2. Description of the Prior Art
Generally, a memory device may be either a volatile memory device or a nonvolatile memory device. In the volatile memory device, new information can be stored with stored, old information erased, whereas in the nonvolatile memory device, "programmed" information is stored permanently.
As a representative of the volatile memory device, there is a random access memory (RAM), which is an array of memory cells that stores information in binary form in which information can be randomly written into, or read out of, each cell as needed. In other words, the RAM is a read-write memory. On the other hand, in a read only memory (ROM), which is a representative of the nonvolatile memory device, "programmed" information is stored in the memory, and only the read operation is performed.
As a nonvolatile memory device, there are also an erasable programmable ROM and an electrically-erasable programmable ROM, in which the stored information is erasable and new information can be reprogrammed. The EPROM and the EEPROM are identical in programming information and are distinct from each other in their erasing operation. In other words, while the EPROM can be erased only with ultraviolet light, the EEPROM can be erased electrically. However, the EPROM and the EEPROM are the same in their fundamental structure and operation.
In scaling an EEPROM or an EPROM device down to deep sub-micron, many problems occur such that, for example, a coupling ratio and a programming speed are lowered. Accordingly, the integration degree becomes restricted.
Hereinafter, the prior art EPROM and EEPROM devices will be discussed along with the problems generated therein for better understanding of the background of the invention, referring to the accompanying drawings and initially to FIG. 1. There is a sectional view showing the structure of a conventional EEPROM cell having a symmetric structure. As shown in FIG. 1, such EEPROM cell includes a semiconductor substrate 11 insulated by an insulating film 12 from a floating gate 13 which is covered with an inter-layer insulating film 14 that insulates a control gate 15 from the floating gate, such substrate having a source region 16 and a drain region 17 therein which are separated by a channel region 18 from the source region 16 and overlaps with the gate 13.
Information is stored in the floating gate 13, which is formed on the channel region 18 defined between the source region 16 and the drain region 17 in the substrate. The mechanism for storing information is that, on applying a voltage at the control gate 15, hot electrons of high energy are generated at the channel region 18 and are then injected by the electric field applied at the control gate 15 into the floating gate 13 through the gate insulating film 12 and stored therein. The information stored in the floating gate 13 can be erased with ultraviolet light.
However, the symmetric EPROM cell in which each of the source region 16 and the drain region 17 overlaps with the channel region has a low coupling ratio and only a little electric current is generated by the hot electrons therein, which do, in turn, generate such a problem that program efficiency decreases. In addition, for the sake of obtaining a large quantity of gate current, a relatively high voltage must be applied at the control gate 15 for programming. However, an implicated external circuit is required to apply the high voltage at the control gate, so that the integration degree of cell may be not heightened sufficiently.
A detailed description will be given next for a conventional method for fabricating a symmetric EPROM device in reference with FIG. 2.
Firstly in step A, over a p-type substrate 21 is formed a pair of gate oxide films 23, on which a pair of gates 25, control gates 29 and inter-layer insulating films 25 between the gates 25 and the control gates 29 are then formed, respectively. Thereafter, a thin insulating film is formed on the entire resultant structure.
Subsequently in step B, a thick insulating film is deposited and is then subjected to an anisotropic etching to form spacers 33 at side walls of the gates.
Step C is undertaken to remove one of the spacers formed at the side walls of the gate. For this, a photoresist film is completely coated and is then subjected to a patterning to form a photoresist pattern 35, exposing the spacer 33 formed at one side wall of the gate.
Lastly in step D, a source region and a drain region are formed. Using the insulating film 31 as an etching stopper, the exposed spacers 33 are removed by applying a dry etching. Thereafter, the photoresist pattern 35 is removed, leaving spacers 33 formed at one side wall of the gate. Following this, n-type dopants are implanted at a high density in the substrate to form impurity regions 37 and 39 therein. For reference, the n.sup.+ type impurity region 37 acts as a source region in the memory cell, whereas the n.sup.+ impurity region 39 acts as a drain region.
In the conventional EPROM device having a stack gate structure, the source region 37 is formed in such an asymmetric structure that the source region 37 overlaps with the gate and the drain region 39 does not overlap with it. In such EPROM device of stack structure, a high voltage at the drain region 39 for programming. The high voltage allows a large quantity of gate current to be generated, so that the programming speed is faster than in the conventional symmetric EPROM device.
However, the conventional method for fabricating an asymmetric EPROM device adopting a photo etching process has a limit in highly integrating a cell since a gate cannot be defined to deep sub-micron with the conventional photo etching process.
In addition, since the coupling ratio between the control gate and the floating gate is low as shown in FIG. 2, there also occurs the problem that programming efficiency decreases.
Turning now to FIG. 3, there is a sectional view showing a conventional asymmetric EEPROM device. The device is formed of a substrate 41 in which a drain region 43 having a shallow junction and a relative deep source region is formed, both defining a channel 44 therebetween. In the device, a gate insulating film 45 is formed over the channel region 44, extending into the drain region 43 and overlapping with a portion of the source region 42. Over the gate insulating film 45 a floating gate 46 is formed which is insulated by an inter-layer insulating film 47 from a control gate 48 in order to provide a high capacitance.
Though the conventional EEPROM cell has an asymmetric structure, it is different from the asymmetric EPROM device of FIG. 2. That is, in the EEPROM device, the source region 42 and the drain region 43 overlap the gate, individually, the former consisting of a shallow junction diffusion region 42-1 and a deep junction diffusion 42-2, and the latter consisting of a single, shallow diffusion region.
In the conventional EEPROM structure, if the drain region 43 is provided with a higher voltage than the source region 42 and the control gate 48 is provided with a relatively much higher voltage, hot electrons are generated in the channel region 44. These hot electrons are then injected, via the gate film 45, into and stored in the floating gate 46. Accordingly, information is programmed in the EEPROM device.
An erasing operation is achieved by floating the drain region 43 and applying a high voltage at the source region 42 with the control gate 48 being maintained with a ground voltage. Under this condition, a tunnelling phenomenon occurs in the overlapping portion between the floating gate 46 and the source region 42, so that the information stored in the floating gate 46 can be erased.
In the conventional EEPROM device, capacitive coupling between the floating gate 46 and the control gate 48 plays an important role in determining the amount of charge that is stored in and drawn out of the floating gate 46. In other words, as the capacitive coupling ratio becomes large, the gate current is generated in large quantities. Accordingly, the programming speed is enhanced.
Since the floating gate and the control gate are in a relation of flat structure in such conventional EEPROM device like the EPROM device of FIG. 2, the gate is required to be lengthened in order to enlarge the overlapping area between the floating gate 46 and the control gate 48. However, the length of gate has influence on the integration degree of the device, so that its size is restrained and thus the overlapping area between the gates is also limited. Accordingly, the coupling ratio decreases, so that the programming speed slows.